There is an increasing demand for nonvolatile storages having a rewritable nonvolatile main memory mainly in semiconductor memory cards. Such semiconductor memory cards include various types, and as one of them, there is a SD memory card. The SD memory card has a flash memory as a nonvolatile main memory and a memory controller for controlling the flash memory. According to instructions for reading and writing from an access device such as a digital still camera, the memory controller controls reading and writing to and from the flash memory.
Since the flash memory used as the main memory of the SD memory card has a limitation on the guaranteed number of times of rewriting such as about one hundred thousand times, a mechanism called as “wear leveling” is employed so that rewriting may not concentrate on a specific area.
The “wear leveling” is a mechanism which prevents concentration of rewriting on a specific area in the flash memory by converting logical addresses given from the access device in order to access the flash memory into physical addresses. Generally, the conversion of logical addresses into physical addresses is executed based on an address management table.
For example, a nonvolatile storage disclosed in Patent document 1 also has an address management table, and the address management table is allocated to a fixed area in a main memory formed of a flash memory.
With this configuration, wear leveling itself works well, but when a rewriting frequency of data is more than a rewriting frequency of the address management table, there has been a problem that the number of times of rewriting on an area to which the address management table is allocated exceeds the guaranteed number of times of rewriting early, thereby the life of a storage is shortened as a whole.
As a technique for solving the problem, a technique described in Patent document 2 is known. In Patent document 2, information rewritten in high frequency such as the address management table is stored in a nonvolatile auxiliary memory such as a ferroelectric memory (FeRAM) with the larger guaranteed number of times of rewriting than that of the flash memory, not in the main memory formed of the flash memory. This is due to that, as shown in Table 1, the FeRAM generally has the many larger guaranteed number of times of rewriting and a faster writing speed in small volume than those of the flash memory.
TABLE 1Flash memoryFeRAMNonvolatileNonvolatileMemory type(10 years)(10 years)Data rewriting unit512 to 2 kbytesOne to several bytesWriting cycleSeveral hundreds μs100 nsGuaranteed numberOne hundredTen billion timesof times ofthousand timesrewritingOverwritingImpossiblePossible
Here, regarding the conventional nonvolatile storage disclosed in Patent document 2, a configuration and an operation thereof will be described, and further, problems will be described, referring to FIGS. 1 to 5.
FIG. 1 is a block diagram of the nonvolatile storage in Patent document 2.
The nonvolatile storage 101 can be accessed from an access device 100 provided outside and includes a memory controller 102 and a nonvolatile main memory 103 formed of the flash memory.
The access device 100 sends commands for reading or writing of data (user data) in the main memory 103 and sends a logical address for performing reading or writing to the memory controller 102, and then, sends or receives data to or from the memory controller 102.
In response to the commands for reading or writing from the access device 100, the memory controller 102 writes data to the main memory 103 or reads data from the main memory 103. The memory controller 102 includes a host I/F part 111, a CPU 112 for controlling the whole memory controller 102, a RAM 113 as a work area of the CPU 112, a ROM 114 for storing a program executed by the CPU 112 therein, and a nonvolatile RAM 117 (nonvolatile auxiliary memory) formed of a ferroelectric memory (FeRAM). The nonvolatile RAM 117 stores a physical area management table 115 and a logical-physical conversion table 116 which are access data used in accessing the main memory 103.
The physical area management table 115 stores a status flag representing a state of a physical block as an erasure unit in the main memory 103, that is, whether or not valid data is stored.
The logical-physical conversion table 116 is a table for converting logical addresses transferred by the access device 100 into physical addresses in the main memory 103.
The memory controller 102 further includes a buffer 118 formed of a volatile RAM such as an SRAM, a read-write control part 119 for reading and writing data in the main memory 103, and an address management information control part 120 for managing addresses of the main memory 103 on the basis of the physical area management table 115 and the logical-physical conversion table 116.
The main memory 103 is composed of a lot of physical blocks. The physical block is an erasure unit, for example, consists of 32 pages as shown in FIG. 2. Each page consists of a data area (512 bytes) of 1 sector and a management area (16 bytes) as a redundant portion.
FIG. 3 shows a format of the logical address given from the access device 100 in a case where a capacity of the main memory 103 is 1 Gbyte. As shown in the figure, a page address and a logical block address are arranged in the order from a lower order bit to higher order, and 16 bits corresponding to the logical block address are the address to be converted, that is, an address in the logical-physical conversion table 116.
Since a sector size is 512 bytes and a cluster size is 16 kbytes defined by a file system of the access device 100, LSB of the cluster number corresponds to bit 5 (b5) in the logical address format.
FIG. 4 is a view showing a format of the physical area management table 115 in the case where the capacity of the main memory 103 is 1 Gbyte. An address in the physical area management table 115 corresponds to the physical block address in the main memory 103. The physical area management table 115 stores a state of each physical block in binary. That is, in the physical area management table 115, a value 00 represents a valid block in which valid data is stored, a value 11 represents an invalid block in which data is erased or unnecessary data is written, and a value 10 represents a bad block which becomes unavailable due to a solid error on a memory cell.
FIG. 5 is a view showing a format of the logical-physical conversion table 116 in the case where the capacity of the main memory 103 is 1 Gbyte. The addresses in the logical-physical conversion table 116 correspond to a logical block address (FIG. 3) of the logical address designated by the access device 100 and contents in the logical-physical conversion table 116 are physical block addresses.
Operations of the nonvolatile storage having the above-mentioned configuration will be described.
Firstly, contents in the main memory 103, physical area management table 115 and logical-physical conversion table 116 of the nonvolatile storage in an initial state, for example, immediately after shipping will be described. For simplification, description of a system area, which is allocated to the main memory 103 and stores a manufacturer code and security information therein, is omitted and only an ordinary area, that is, an area where a user reads and writes data will be described.
In the initial state, all of good blocks of the main memory 103 are erased. In other words, in the physical area management table 115, the value 11 in binary is set to a good block as an invalid block state and the value 10 in binary is set to an initial bad block as a bad block.
A value FFFF in hexadecimal is set to each address in the logical-physical conversion table 116. The value FFFF means that no physical address is set, not that the physical address in the main memory 103 is the address FFFF. Accordingly, the physical address FFFF address in the main memory 103 indicates an unavailable physical block, and a logical address space managed by the access device 100 is less than 65536 addresses from an address 0000 to an address FFFF.
After the nonvolatile storage is powered on, the CPU 112 performs initialization processing on the basis of a program stored in the ROM 114. Following the initialization processing, the nonvolatile storage is ready to accept commands for reading, writing, and the like from the access device 600.
Considered is a case where an instruction for writing to an arbitrary logical address is made in units of clusters from the access device 600.
When the instruction for writing is issued, based on the logical address, the address management information control part 120 searches invalid physical blocks in descending order from a predetermined address in the physical area management table 115 and the invalid physical block firstly found is to be a physical block to be written. Data of 1 cluster is written to the block to be written after data already existing in the block is erased.
The above-mentioned predetermined address is an address sequentially set to the address management information control part 120 by the CPU 112 so as to vary at random at each setting. Herewith, a wear leveling for preventing the block to be written from concentrating on a specific physical block is realized.
After the data is written to the main memory 103, in the physical area management table 115, a status flag of the physical block to which the data is written is set as the “valid block”. In the logical-physical conversion table 116, at a position of the logical address designated according to the instruction for writing, a value of physical address corresponding to the address is written.
When a rewriting command is issued from the access device 100, in addition to the above-mentioned processing, a physical block in which old data is stored is identified based on the logical-physical conversion table 116, and the status flag in the physical area management table 115 which corresponds to the physical address of the old data is set as an invalid block.
As mentioned above, each time in writing or rewriting by the access device 100, the physical area management table 115 and the logical-physical conversion table 116 stored in the nonvolatile RAM 117 are referred and updated. Thus, the number of times of referring and updating of the nonvolatile RAM 117 is considered. Note that a capacity of the main memory 103 is assumed to be a large capacity of 4 GB.
For example, rewriting of the main memory 103 by each 1 cluster (=1 physical block) of 16 kbytes will be considered below. In this case, each time rewriting for 1 cluster is performed, the physical area management table 115 and the logical-physical conversion table 116 held in the nonvolatile RAM 117 are read multiple times and rewritten once on average. Accordingly, at a time when the main memory 103 is rewritten one hundred thousand times, in other words, at the guaranteed number of times of rewriting of the flash memory, the physical area management table 115 and others are considered to be also rewritten about one hundred thousand times.
The nonvolatile RAM 117 storing the tables 115, 116 therein is formed of FeRAM and is a memory device whose guaranteed number of times of rewriting is ten billion. Therefore, it has been considered that, even under any situation, the number of times of rewriting of the nonvolatile RAM 117 never reaches the guaranteed number of times of rewriting faster than that of the main memory 103.    Patent document 1: Japanese Unexamined Patent Publication No. 2001-142774    Patent document 2: Japanese Unexamined Patent Publication No. Hei 07-219720